Takashi NAKADA


An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation
Takashi NAKADA Tomoki HATANAKA Hiroshi UEKI Masanori HAYASHIKOSHI Toru SHIMIZU Hiroshi NAKAMURA 
Publication:   
Publication Date: 2017/10/01
Vol. E100-D  No. 10  pp. 2493-2504
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
adaptive task schedulingnear real-time processingexecution time variationenergy efficiency
 Summary | Full Text:PDF(904.3KB)

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip
Yuan HE Masaaki KONDO Takashi NAKADA Hiroshi SASAKI Shinobu MIWA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2881-2890
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
Networks-on-Chipperformanceenergy efficiencyoptimizationselection
 Summary | Full Text:PDF(1.7MB)

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction
Jun YAO Yasuhiko NAKASHIMA Naveen DEVISETTI Kazuhiro YOSHIMURA Takashi NAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12  pp. 3092-3100
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
reconfigurable architecturesmulti-core processingenergy efficiency
 Summary | Full Text:PDF(1.2MB)

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path
Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2319-2329
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
adaptive redundancysetup error recoveryDVSlow powerAVF
 Summary | Full Text:PDF(4.1MB)

An Instruction Mapping Scheme for FU Array Accelerator
Kazuhiro YOSHIMURA Takuya IWAKAMI Takashi NAKADA Jun YAO Hajime SHIMADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2  pp. 286-297
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
instruction mappingFU arraycoarse-grained reconfigurable architecture
 Summary | Full Text:PDF(3.6MB)