Takashi HORI


Enumerating All Spanning Shortest Path Forests with Distance and Capacity Constraints
Yu NAKAHATA Jun KAWAHARA Takashi HORIYAMA Shoji KASAHARA 
Publication:   
Publication Date: 2018/09/01
Vol. E101-A  No. 9  pp. 1363-1374
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithmgraph partitioningdecision diagramfrontier-based searchenumeration problem
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Rep-Cubes: Dissection of a Cube into Nets
Dawei XU Jinfeng HUANG Yuta NAKANE Tomoo YOKOYAMA Takashi HORIYAMA Ryuhei UEHARA 
Publication:   
Publication Date: 2018/09/01
Vol. E101-A  No. 9  pp. 1420-1430
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
cubenetpolyominopythagorean triplerep-cuberep-tile
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Computational Complexity of Piano-Hinged Dissections
Zachary ABEL Erik D. DEMAINE Martin L. DEMAINE Takashi HORIYAMA Ryuhei UEHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/06/01
Vol. E97-A  No. 6  pp. 1206-1212
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
GeoLoophinged dissectionIvan's HingeNP-hardnesspaper folding
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FOREWORD
Takashi HORIYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/03/01
Vol. E96-D  No. 3  pp. 399-399
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1347-1358
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
actual power reductionautomatic multi-stage clock gating optimizationILP formulationswitching activityBDDMIP optimizer
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Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2472-2480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
automatic clock gating generationlow powerdynamic power reductionBDD
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Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3531-3538
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
power gatingmulti-threshold CMOS (MTCMOS) technologyBDDcontrolling valueleakage power reduction
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New Graph Calculi for Planar Non-3-Colorable Graphs
Yoichi HANATANI Takashi HORIYAMA Kazuo IWAMA Suguru TAMAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9  pp. 2301-2307
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
Hajos calculusplanar graphcoloringproof systems
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Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3427-3434
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
HDLhigh-level synthesisbit-length optimizationnon-linear programming
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Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3184-3191
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
HDLhigh-level synthesisparallelizing compilerbit length
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Look Up Table Compaction Based on Folding of Logic Functions
Shinji KIMURA Atsushi ISHII Takashi HORIYAMA Masaki NAKANISHI Hirotsugu KAJIHARA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2701-2707
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
field programmable gate array (FPGA)LUT architecturereconfigurable logic
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Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division
Takashi HORIYAMA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/08/25
Vol. E81-D  No. 8  pp. 793-800
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
Boolean functiondivisionbinary decision diagramslower boundfooling set
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C-V and I-V Characteristics of a MOSFET with Si-Implanted Gate-SiO2
Takashi OHZONE Takashi HORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/06/25
Vol. E77-C  No. 6  pp. 952-959
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
MOSFETSi-implantationEEPROM
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LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs
Junji HIRASE Takashi HORI Yoshinori ODAKE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3  pp. 350-354
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
MOSFETLDDn--gate overlapcircuit speedhot-carrier-induced degradation
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Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM
Masanori FUKUMOTO Yasushi NAITO Kazuhiro MATSUYAMA Hisashi OGAWA Koji MATSUOKA Takashi HORI Hiroyuki SAKAI Ichiro NAKAO Hisakazu KOTANI Hiroshi IWASAKI Michihiro INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 818-826
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
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