Takanori SHIRAI


Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits
Kazuya SHIMIZU Takanori SHIRAI Masaya TAKAMURA Noriyoshi ITAZAKI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1526-1533
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
domino circuitcrosstalk faulttarget fault reductionfault simulation
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