Takahiro ONAI


High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology
Hiromi SHIMAMOTO Takahiro ONAI Eiji OHUE Masamichi TANABE Katsuyoshi WASHIO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Vol. E82-C  No. 11  pp. 2007-2012
Type of Manuscript:  Special Section PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)
Category: Low Power-Consumption RF ICs
Keyword: 
silicon bipolar transistornoise figureoptical communicationwireless communication
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Test Structure and Experimental Analysis of Emitter-Base Reverse Voltage Stress Degradation in Self-Aligned Bipolar Transistors
Hiromi SHIMAMOTO Masamichi TANABE Takahiro ONAI Katsuyoshi WASHIO Tohru NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 211-218
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Reliability Analysis
Keyword: 
self-aligned bipolar transistorhot-carrieremitter-base reverse voltage stress
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Simplified Distribution Base Resistance Model in Self-Aligned Bipolar Transistors
Masamichi TANABE Hiromi SHIMAMOTO Takahiro ONAI Katsuyoshi WASHIO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 165-171
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Device and Circuit Characterization
Keyword: 
self-aligned bipolar transistorbase resistanceparasitic base resistancespreading resistance
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Process and Device Technologies for High Speed Self-Aligned Bipolar Transistors
Tohru NAKAMURA Takeo SHIBA Takahiro ONAI Takashi UCHINO Yukihiro KIYOTA Katsuyoshi WASHIO Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1154-1164
Type of Manuscript:  INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices)
Category: 
Keyword: 
silicon bipolardouble polysiliconhigh speedself-alignment
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Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs
Youji IDEI Takeo SHIBA Noriyuki HOMMA Kunihiko YAMAGUCHI Tohru NAKAMURA Takahiro ONAI Youichi TAMAKI Yoshiaki SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1369-1376
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
soft errorSICOSbipolar RAM256 Kbit
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