IEICE SEARCH SYSTEM

Takaaki OKUMURA

Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/10/01 Vol. E94-A No. 10 pp. 1948-1953 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, Flip-Flop, setup time, hold time, timing analysis,
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Gate Delay Estimation in STA under Dynamic Power Supply Noise Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2447-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power supply noise, gate delay, timing analysis,
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Impact of Self-Heating in Wire Interconnection on Timing Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 388-392 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC,
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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3016-3023 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: low power, leakage, gate delay model, variation,
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Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 990-997 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, output, transition time, gate delay model, process variation,
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Proposal of Metrics for SSTA Accuracy Evaluation Hiroyuki KOBAYASHI Nobuto ONO Takashi SATO Jiro IWAI Hidenari NAKASHIMA Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 808-814 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: statistical static timing analysis, statistical max operation, DFM, SoC,
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A Method to Derive SSO Design Rule Considering Jitter Constraint Koutaro HACHIYA Hiroyuki KOBAYASHI Takaaki OKUMURA Takashi SATO Hiroki OKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 865-872 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: simultaneous switching output, simultaneous switching noise, jitter, ASIC,
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