Taisuke MATSUMOTO

High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors
Yutaka ARAYASHIKI Takashi KAMIZONO Yukio OHKUBO Taisuke MATSUMOTO Yoshiaki AMANO Yutaka MATSUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6  pp. 912-919
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
DHBT, MUX, DEMUX, G-CPW, module, 
 Summary | Full Text:PDF(3.3MB)
A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
Yutaka ARAYASHIKI Yukio OHKUBO Taisuke MATSUMOTO Yoshiaki AMANO Akio TAKAGI Yutaka MATSUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1273-1278
Type of Manuscript:  Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2009)
Category: III-V High-Speed Devices and Circuits
Keyword: 
DHBT, self-aligned, ledge, MUX, broadband impedance matching, module, 
 Summary | Full Text:PDF(981.9KB)