Tae Whan KIM

Multilevel Dual-Channel NAND Flash Memories with High Read and Program Verifying Speeds Utilizing Asymmetrically-Doped Channel Regions
Joung Woo LEE Joo Hyung YOU Sang Hyun JANG Kae Dal KWACK Tae Whan KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 654-657
Type of Manuscript:  BRIEF PAPER
Category: Memory Devices
Keyword: 
NAND flash memory, multilevel dual-channel, high-speed multilevel reading, current sensing, and high-speed program verifying, 
 Summary | Full Text:PDF(2.1MB)
Enhancement of the Programming Speed in SANOS Nonvolatile Memory Device Designed Utilizing Al2O3 and SiO2 Stacked Tunneling Layers
Hyun Woo KIM Dong Hun KIM Joo Hyung YOU Tae Whan KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 651-653
Type of Manuscript:  BRIEF PAPER
Category: Memory Devices
Keyword: 
SANOS, SONOS, charge transport, silicon nitride, stacked tunneling layer, 
 Summary | Full Text:PDF(508.6KB)
A Design of Temperature-Compensated Complementary Metal-Oxide Semiconductor Voltage Reference Sources with a Small Temperature Coefficient
Kyung Soo PARK Sun Bo WOO Kae Dal KWACK Tae Whan KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 751-755
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
1st order voltage reference, temperature compensation, temperature coefficient, nonlinearity of base-emitter voltage, 
 Summary | Full Text:PDF(362.9KB)