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A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A2BC)” Tadayoshi ENOMOTO Nobuaki KOBAYASHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C
No. 4
pp. 424-432
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: multimedia, H.264/AVC, motion estimation, DVFS, power dissipation, DC/DC level converter, | | Summary | Full Text:PDF | |
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A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM Tadayoshi ENOMOTO Nobuaki KOBAYASHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C
No. 4
pp. 530-538
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Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: SRAM, leakage power, “write” margin, “read” margin, | | Summary | Full Text:PDF | |
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Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit Tadayoshi ENOMOTO Nobuaki KOBAYASHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C
No. 4
pp. 409-416
Type of Manuscript:
Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: clocks, CMOS digital circuits, power consumption, SPICE, | | Summary | Full Text:PDF | |
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FOREWORD Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C
No. 4
pp. 385-385
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FOREWORD Category: Keyword:
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Designs of Building Blocks for High-Speed, Low-Power Processors Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2
pp. 331-338
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: High-Performance Technologies Keyword: register file, cache SRAM, GaAs, power dissipation, | | Summary | Full Text:PDF | |
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Low Power Design Technology for Digital LSIs Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C
No. 12
pp. 1639-1649
Type of Manuscript:
INVITED PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: power dissipation, active power dissipation, stand-by power dissipation, low power circuit technology, LSI, CMOS LSIs, GaAs LSIs, mlulti-media LSIs, video codec LSIs, signal handling capability, throughput, clock frequency, video signal processor, VSP, DSP. H.261, MPEG2, | | Summary | Full Text:PDF | |
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FOREWORD Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C
No. 12
pp. 1637-1638
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FOREWORD Category: Keyword:
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High-Throughput Technologies for Video Signal Processor (VSP) LSIs Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C
No. 4
pp. 459-471
Type of Manuscript:
INVITED PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: video codec LSIs, video signal processor, VSP, DSP, video data encoding, decoding, H.261, MPEG2, power dissipation, throughtput, | | Summary | Full Text:PDF | |
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FOREWORD Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C
No. 12
pp. 1653-1654
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FOREWORD Category: Keyword:
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A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12
pp. 1951-1956
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Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs) Category: Processor Interfaces Keyword: electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP, | | Summary | Full Text:PDF | |
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Design of a 3.2 GHz 50 mW 0.5 µm GaAs PLL-Based Clock Generator with 1 V Power Supply Tadayoshi ENOMOTO Toshiyuki OKUYAMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12
pp. 1957-1965
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs) Category: Processor Interfaces Keyword: phase-locked loop (PLL), clock pulse generator (CG), voltage controlled ring oscillater (VCO), VCO gain, GaAs, MESFET, DCFL circuit, pull-in frequency, pull-in range, pull-in time, lock range, lock time, locked state, | | Summary | Full Text:PDF | |
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FOREWORD Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C
No. 12
pp. 1711-1712
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FOREWORD Category: Keyword:
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Reviews and Prospects of SRAM Technology Masahide TAKADA Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C
No. 4
pp. 827-838
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INVITED PAPER (Special Issue on LSI Memories) Category: SRAM Keyword:
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Floating Gate Tapped CCD and Its Minimum Phase Lowpass Transversal Filter Application Tadayoshi ENOMOTO Masaaki YASUMOTO Shigeo FUSHIMI | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1979/10/25
Vol. E62-E
No. 10
pp. 666-667
Type of Manuscript:
LETTER Category: Integrated Circuits Keyword:
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