IEICE Trans

Tadato YAMAGATA

Large Scale Embedded DRAM Technology Akira YAMAZAKI Tadato YAMAGATA Yutaka ARITA Makoto TANIGUCHI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 pp. 750-758 Type of Manuscript: INVITED PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: DRAM Keyword: embedded DRAM, system on chip, system LSI,
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A Long Data Retention SOI DRAM with the Body Refresh Function Shigeki TOMISHIMA Fukashi MORISHITA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 899-904 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Structure Devices Keyword: memory, SOI-DRAM, body region, refresh, data retention,
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SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories Shigehiro KUGE Fukashi MORISHITA Takahiro TSURUDA Shigeki TOMISHIMA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 997-1002 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs Shigeki TOMISHIMA Shigehiro KUGE Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 808-811 Type of Manuscript: Special Section LETTER (Special Issue on ULSI Memory Technology) Category: Dynamic RAMs Keyword: memory, triple metal, source line, layout,
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A Flexible Search Managing Circuitry for High-Density Dynamic CAMs Takeshi HAMAMOTO Tadato YAMAGATA Masaaki MIHARA Yasumitsu MURAI Toshifumi KOBAYASHI Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1377-1384 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: General Technology Keyword: content addressable memory, associative memory, dynamic memory, functional memory,
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A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA Masaaki MIHARA Takeshi HAMAMOTO Yasumitsu MURAI Toshifumi KOBAYASHI Michihiro YAMADA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1657-1664 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content addressable memory, associative memory, dynamic memory, redundancy,
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