Tadahiko SUGIBAYASHI


Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
Ryusuke NEBASHI Noboru SAKIMURA Tadahiko SUGIBAYASHI Naoki KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 417-422
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
MRAMembedded memorySoCsystem LSI
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MRAM Applications Using Unlimited Write Endurance
Tadahiko SUGIBAYASHI Takeshi HONDA Noboru SAKIMURA Shuichi TAHARA Naoki KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1936-1940
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Next-Generation Memory for SoC
Keyword: 
MRAMdrive recorderasynchronous SRAMpseudo SRAMdemo system
 Summary | Full Text:PDF

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode
Takeshi HONDA Noboru SAKIMURA Tadahiko SUGIBAYASHI Naoki KASAI Hiromitsu HADA Shu-ichi TAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/02/01
Vol. E90-C  No. 2  pp. 531-535
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
MRAMtoggleintermittent failure
 Summary | Full Text:PDF

MRAM Writing Circuitry to Compensate for Thermal Variation of Magnetization Reversal Current
Takeshi HONDA Noboru SAKIMURA Tadahiko SUGIBAYASHI Hideaki NUMATA Sadahiko MIURA Hiromitsu HADA Shuichi TAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 612-617
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
MRAMmagnetization reversal currentthermal-variation compensation
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Hierarchical Word-Line Architecture for Large Capacity DRAMs
Tatsunori MUROTANI Tadahiko SUGIBAYASHI Masahide TAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 550-556
Type of Manuscript:  INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: Memory LSI
Keyword: 
DRAMhierarchical word linepartial subarray activation
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A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 787-791
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMhierarchical bit-linerefresh
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A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI Isao NARITAKE Hiroshi TAKADA Ken INOUE Ichiro YAMAMOTO Tatsuya MATANO Mamoru FUJITA Yoshiharu AIMOTO Toshio TAKESHIMA Satoshi UTSUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1323-1327
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memoryDRAMtest
 Summary | Full Text:PDF