Susumu KOBAYASHI


A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations
Susumu KOBAYASHI Fumihiro MINAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1980-1985
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
clock skewinterconnectprocess variationsignal delay
 Summary | Full Text:PDF(1.3MB)

An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio
Susumu KOBAYASHI Naoshi DOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 492-499
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
decoupling capacitancepower supply noisepower dissipationlayout designsimulation
 Summary | Full Text:PDF(754.2KB)

A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths
Susumu KOBAYASHI Masato EDAHIRO Mikio KUBO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2499-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSI CADscan-chainlayout designdesign for testability
 Summary | Full Text:PDF(736.9KB)