Suki KIM

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
Jeonghun KIM Suki KIM Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/09/01
Vol. E93-D  No. 9  pp. 2500-2508
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
Bluetooth V2.0, enhanced data rate (EDR), low-power architecture, wireless SOC, sub band codec, platform-based design, verification, 
 Summary | Full Text:PDF
6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator
Yun-Jeong KIM Jong-Ho LEE Ja-Hyun KOO Kwang-Hyun BAEK Suki KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3  pp. 392-395
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
comparator, flash ADC, high-speed ADC, interpolation, 
 Summary | Full Text:PDF
Digitally Controlled Duty Cycle Corrector with 1 ps Resolution
Youngkwon JO Hoyoung PARK Sanghyuk YANG Suki KIM Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/09/01
Vol. E90-C  No. 9  pp. 1841-1843
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
duty cycle corrector, variable delay unit, delay locked loop, 
 Summary | Full Text:PDF
A Low Jitter ADPLL for Mobile Applications
Kwang-Jin LEE Hyo-Chang KIM Uk-Rae CHO Hyun-Geun BYUN Suki KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6  pp. 1241-1247
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
Keyword: 
ADPLL, All Digital PLL, DCO, 
 Summary | Full Text:PDF