Suk-Jin KIM


A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques
Jeong-Gun LEE Wook SHIN Suk-Jin KIM Eun-Gu JUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/06/01
Vol. E93-A  No. 6  pp. 1215-1225
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multi-coreenergy/performanceasymptotic analysisAmdahl's lawRent's rule
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Design of a Mutated Adder and Its Optimization Using ILP Formulation
Jeong-Gun LEE Jeong-A LEE Suk-Jin KIM Kiseon KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1506-1508
Type of Manuscript:  Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
mutated addermixture of carry propagation schemesILP-based optimization
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Low Latency Four-Flop Synchronizer with the Handshake Interface
Suk-Jin KIM Jeong-Gun LEE Kiseon KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1460-1463
Type of Manuscript:  Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Communications and Wireless Systems
Keyword: 
synchronizertwo-flopclock domainSoC
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A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme
Jeong-Gun LEE Suk-Jin KIM Jeong-A LEE Kiseon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 1031-1037
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
asynchronous FIFOwave pipelinelinear structureforward latencythroughput
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A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains
Suk-Jin KIM Jeong-Gun LEE Kiseon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3166-3173
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
synchronizertwo-flopmetastabilityclock domain
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Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure
Chan-Ho PARK Byung-Soo CHOI Suk-Jin KIM Eun-Gu JUNG Dong-Ik LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/07/01
Vol. E86-D  No. 7  pp. 1243-1249
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
array multiplierWallace treecarry save adderasynchronous multiplierasynchronous design method
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