Stefan HOLST


Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang LI Xiaoqing WEN Kohei MIYASE Stefan HOLST Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2310-2319
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
at-speed scan testingIR-dropcapture-power-safetylogic pathclock pathclock stretchtest quality
 Summary | Full Text:PDF

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Akihiro TOMITA Xiaoqing WEN Yasuo SATO Seiji KAJIHARA Kohei MIYASE Stefan HOLST Patrick GIRARD Mohammad TEHRANIPOOR Laung-Terng WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10  pp. 2706-2718
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
at-speed scan-based logic BISTcapture power safetymaskingIR-droptransition delay faultlong sensitized path
 Summary | Full Text:PDF