Soon-Jyh CHANG


A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder
I-Jen CHAO Ching-Wen HOU Bin-Da LIU Soon-Jyh CHANG Chun-Yueh HUANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6  pp. 526-537
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
delta-sigma modulatorDSMopamp sharingrelaxed dynamic element matching (DEM) timing
 Summary | Full Text:PDF(3.5MB)

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs
An-Sheng CHAO Cheng-Wu LIN Hsin-Wen TING Soon-Jyh CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6  pp. 538-545
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
analog-to-digital converter (ADC)design for testability (DFT)pattern generator (PG)output response analyzer (ORA)
 Summary | Full Text:PDF(2.1MB)

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding
Ya-Ting SHYU Ying-Zu LIN Rong-Sing CHU Guan-Ying HUANG Soon-Jyh CHANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2415-2423
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
built-in self-test (BIST)bit error rate (BER)analog-to-digital converter (ADC)
 Summary | Full Text:PDF(2.5MB)

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages
Jin-Fu LIN Soon-Jyh CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1  pp. 89-101
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
analog-to-digital converter (ADC)data convertercorrelated double sampling (CDS)time-interleavedsuccessive approximation (SA) ADC
 Summary | Full Text:PDF(1.6MB)

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process
Ying-Zu LIN Soon-Jyh CHANG Yen-Ting LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/02/01
Vol. E92-C  No. 2  pp. 258-268
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
flash A/D converterhigh-speed data converterinterpolationresistive averaging network
 Summary | Full Text:PDF(1MB)

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture
Hsin-Hung OU Bin-Da LIU Soon-Jyh CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1480-1487
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
switched-opamplow-voltagehigh-speedsample-and-holddouble-sampling
 Summary | Full Text:PDF(378.4KB)

A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter
Chia-Ling WEI Lu-Yao WU Hsiu-Hui YANG Chien-Hung TSAI Bin-Da LIU Soon-Jyh CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 809-812
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
DC-DC converterswitched-capacitorstep upstep downefficiency
 Summary | Full Text:PDF(136.6KB)

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture
Hsin-Hung OU Soon-Jyh CHANG Bin-Da LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 461-468
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
low-voltageswitched-opampsample-and-holdopamp-sharingpipelined ADC
 Summary | Full Text:PDF(498.3KB)