Soo-Ik CHAE


Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator
Daewoong KIM Kilhyung CHA Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/07/01
Vol. E92-D  No. 7  pp. 1500-1502
Type of Manuscript:  LETTER
Category: Computer Graphics
Keyword: 
OpenVGtwo-dimensional vector graphicsadaptivescanline fillingscanning directionskew
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VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
Jinhyun CHO Doowon LEE Sangyong YOON Sanggyu PARK Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/01/01
Vol. E92-A  No. 1  pp. 279-290
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SMPTE 421M-2006 VC-1video decodertransaction level modelingdesign space exploration
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Cache Optimization for H.264/AVC Motion Compensation
Sangyong YOON Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12  pp. 2902-2905
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
cacheH.264motion compensationmemory bandwidthDDR SDRAM
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A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications
Seokkee KIM Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/05/01
Vol. E89-C  No. 5  pp. 649-652
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
bootstrapped nMOS switchnMOS reversible energy recovery logic (nRERL)adiabatic microprocessor
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A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores
Jeong-Min KIM Yun-Su SHIN In-Gu HWANG Kwang-Sun LEE Sang-Il HAN Sang-Gyu PARK Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 183-192
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLIWmedia processorvideophone
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Reversible Energy Recovery Logic Circuits and Its 8-Phase Clocked Power Generator for Ultra-Low-Power Applications
Joonho LIM Dong-Gyu KIM Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4  pp. 646-653
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
reversible logicadiabatic circuitclocked power generatorreversible energy recovery logic (RERL)
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