IEICE SEARCH SYSTEM

Song CHEN

Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis Nan WANG Song CHEN Wei ZHONG Nan LIU Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/08/01 Vol. E97-A No. 8 pp. 1709-1719 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: mobility overlap removal, dual-V_th, leakage power, register usage, high-level synthesis,
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Leakage Power Aware Scheduling in High-Level Synthesis Nan WANG Song CHEN Cong HAO Haoran ZHANG Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/04/01 Vol. E97-A No. 4 pp. 940-951 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dual-V_th, leakage power, max-flow min-cut,
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Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips Wei ZHONG Song CHEN Bo HUANG Takeshi YOSHIMURA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1174-1184 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: networks on chip (NoC), topology synthesis, floorplanning,
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Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs Nan LIU Song CHEN Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 501-510 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: resource-aware, multi-layer floorlanning, reconfigurable,
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Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2208-2219 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: dual-vdd, min-cut, voltage assignment, low power, timing constraints,
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Floorplanning for High Utilization of Heterogeneous FPGAs Nan LIU Song CHEN Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/09/01 Vol. E95-A No. 9 pp. 1529-1537 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: field programmable gate array, floorplanning, high utilization,
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Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips Wei ZHONG Takeshi YOSHIMURA Bei YU Song CHEN Sheqin DONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 534-545 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: networks on chip (NoC), placement, synthesis, topology,
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Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density Song CHEN Jianwei SHEN Wei GUO Mei-Fang CHIANG Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2372-2379 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: redundant via, double via, design for manufacturability, via density,
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Voltage and Level-Shifter Assignment Driven Floorplanning Bei YU Sheqin DONG Song CHEN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 2990-2997 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Desing Keyword: voltage-island, voltage assignment, convex network flow, level shifter assignment, white space redistribution,
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Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs Song CHEN Liangwei GE Mei-Fang CHIANG Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1080-1087 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: three dimensional integrated circuits, through-the-silicon via, via assignment,
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Max-Flow Scheduling in High-Level Synthesis Liangwei GE Song CHEN Kazutoshi WAKABAYASHI Takashi TAKENAKA Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/09/01 Vol. E90-A No. 9 pp. 1940-1948 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scheduling, high-level synthesis, power-ground integrity,
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VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing Sheqin DONG Xianlong HONG Song CHEN Xin QI Ruijie WANG Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3136-3147 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Place and Routing Keyword: floorplan, placement, solution space smoothing,
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Semi-Automatic Tool for Aligning a Parameterized CAD Model to Stereo Image Pairs Chu-Song CHEN Kuan-Chung HUNG Yi-Ping HUNG Lin-Lin CHEN Chiou-Shann FUH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/12/25 Vol. E82-D No. 12 pp. 1582-1588 Type of Manuscript: PAPER Category: Image Processing,Computer Graphics and Pattern Recognition Keyword: computer vision, rough CAD model, 3D reconstruction,
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Extraction of Corner-Edge-Surface Structure from Range Images Using Mathematical Morphology Chu-Song CHEN Yi-Ping HUNG Ja-Ling WU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/12/25 Vol. E78-D No. 12 pp. 1636-1641 Type of Manuscript: Special Section PAPER (Special Issue on Machine Vision Applications) Category: Keyword: machine vision algorithms, feature extraction, rangedata/3D shapes,
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