IEICE Trans

Shuzo YAJIMA

Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division Takashi HORIYAMA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/08/25 Vol. E81-D No. 8 pp. 793-800 Type of Manuscript: PAPER Category: Algorithm and Computational Complexity Keyword: Boolean function, division, binary decision diagrams, lower bound, fooling set,
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Manipulation of Large-Scale Polynomials Using BMDs Dror ROTTER Kiyoharu HAMAGUCHI Shin-ichi MINATO Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1774-1781 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: zero-suppressed binary decision diagrams (BDD), binary moment diagrams, polynomials,
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Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/04/25 Vol. E80-A No. 4 pp. 663-669 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: computational complexity, Boolean function, ordered binary decision diagram, satisfiability, combinational circuit, cutwidth, sum-of-product form, zero-suppressed binary decision diagrams (BDD), ternary decision diagram,
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Formal Design Verification of Combinational Circuits Specified by Recurrence Equations Hiroyuki OCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/25 Vol. E79-D No. 10 pp. 1431-1435 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Design Verification Keyword: formal design verification, binary decision diagram, arithmetic circuits, specification, recurrence equations,
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The Complexity of the Optimal Variable Ordering Problems of a Shared Binary Decision Diagram Seiichiro TANI Kiyoharu HAMAGUCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/04/25 Vol. E79-D No. 4 pp. 271-281 Type of Manuscript: PAPER Category: Algorithm and Computational Complexity Keyword: ordered binary decision diagram, variable ordering, optimal linear arrangement, NP-complete, Boolean function,
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On the Computational Power of Binary Decision Diagrams Hiroshi SAWADA Yasuhiko TAKENAGA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/06/25 Vol. E77-D No. 6 pp. 611-618 Type of Manuscript: PAPER Category: Automata, Languages and Theory of Computing Keyword: binary decision diagram, on-line Turing machine, planer circuit, permutation, complete language,
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Computational Complexity of Manipulating Binary Decision Diagrams Yasuhiko TAKENAGA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/06/25 Vol. E77-D No. 6 pp. 642-647 Type of Manuscript: PAPER Category: Algorithm and Computational Complexity Keyword: binary decision diagram, computatioal complexity, Boolean function, parallel algorithm,
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Compact Test Sequences for Scan-Based Sequential Circuits Hiroyuki HIGUCHI Kiyoharu HAMAGUCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1676-1683 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: test generation, scan design, test application time, boolean function manipulation,
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Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1121-1127 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Test Keyword: test generation, combinational circuits, compact test sets, binary decision diagrams,
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Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1220-1229 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: design verification, sequential machines, temporal logic, model checking, binary decision diagram,
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Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits Nagisa ISHIURA Yutaka DEGUCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1247-1254 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic circuits, timing verification, symbolic simulation, Boolean function manipulation,
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Linear Time Fault Simulation Algorithm Using a Content Addressable Memory Nagisa ISHIURA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 pp. 314-320 Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: fault simulation, content addressable memory, parallel computation,
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Computational Power of Memory-Based Parallel Computation Models with Communication Yasuhiko TAKENAGA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/01/25 Vol. E75-D No. 1 pp. 89-94 Type of Manuscript: Special Section PAPER (Special Section on Theoretical Foundations of Computing) Category: Keyword: parallel computation model, computational power, hypercube network, functional memory, memory-based parallel computation,
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Properties of Embedded Multivalued Dependencies in Relational Databases Katsumi TANAKA Yahiko KAMBAYASHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1979/08/25 Vol. E62-E No. 8 pp. 536-543 Type of Manuscript: PAPER Category: Data Processing Keyword:
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Reshaping of Power Spectra of Digital Coded Signals by Restricting Inputs to Encoding Automata Susumu YOSHIDA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1977/12/25 Vol. E60-E No. 12 pp. 715-722 Type of Manuscript: PAPER Category: Communication Theory Keyword:
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On the Relation between an Encoding Automaton and the Power Spectrum of Its Output Sequence Susumu YOSHIDA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1976/05/25 Vol. E59-E No. 5 pp. 1-7 Type of Manuscript: PAPER Category: Information Theory Keyword:
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