Shuping ZHANG

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 223-231
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
3D IC design, motion estimation processor, hamburger architecture, memory stacking, 
 Summary | Full Text:PDF(1.6MB)
A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform
Heming SUN Dajiang ZHOU Shuping ZHANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2375-2387
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
HEVC, de-quantization, inverse transform, low-power, low-cost, video coding, 
 Summary | Full Text:PDF(3MB)
Low-Power Motion Estimation Processor with 3D Stacked Memory
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1431-1441
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
3DIC design, motion estimation processor, low power design, memory stacking, 
 Summary | Full Text:PDF(4.1MB)