IEICE Trans

Shuji TSUKIYAMA

A New Algorithm to Determine Covariance in Statistical Maximum for Gaussian Mixture Model Daiki AZUMA Shuji TSUKIYAMA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2834-2841 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: statistical maximum, Gaussian mixture model, covariance, sensitivity, performance evaluation,
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A New Algorithm for Reducing Components of a Gaussian Mixture Model Naoya YOKOYAMA Daiki AZUMA Shuji TSUKIYAMA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2425-2434 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Gaussian mixture model, reduction of components, normalized integral square error, sensitivity, statistical method,
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A New Delay Distribution Model with a Half Triangular Distribution for Statistical Static Timing Analysis Shuji TSUKIYAMA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2542-2552 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: distribution model, half triangular distribution, long-term degradations, statistical maximum, mixture model, non-Gaussian distr ibution, statistical static timing analysis,
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A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve Shuji TSUKIYAMA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2528-2536 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical maximum, Gaussian mixture model, cumulative distribution function curve, statistical static timing analysis,
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A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together Shingo TAKAHASHI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/03/01 Vol. E92-A No. 3 pp. 900-911 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: statistical timing analysis, Gaussian mixture model, delay distribution, slew distribution, variability,
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A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop Yoshiyuki KAWAKAMI Makoto TERAO Masahiro FUKUI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3423-3430 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power grid optimization, timing violation, critical path, process variation, IR drop,
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Transistor Sizing of LCD Driver Circuit for Technology Migration Masanori HASHIMOTO Takahito IJICHI Shingo TAKAHASHI Shuji TSUKIYAMA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2712-2717 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: technology migration, transistor sizing, LCD driver circuit,
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A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays Shingo TAKAHASHI Shuji TSUKIYAMA Masanori HASHIMOTO Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3538-3545 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: active matrix LCD, CAD tool, column driver, sampling pulse, sampling switch,
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An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis Shuji TSUKIYAMA Masahiko TOMITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 pp. 535-543 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: correlation coefficient, interconnect delay, Elmore delay, statistical timing analysis, Gaussian distribution,
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Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2923-2932 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, LCD, parasitic capacitance, signal integrity, circuit simulation,
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An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays Shuji TSUKIYAMA Masakazu TANAKA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2746-2754 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: static timing analysis, statistical approach, correlation, normal distribution, CMOS combinatorial circuits,
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An Algorithm to Position Fictitious Terminals on Borders of Divided Routing Areas Atsushi KAMOSHIDA Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2424-2430 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: fictitious terminal, assignment problem, net crossing, parallel router, multilayer SOG,
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Generation of Minimal Separating Sets of a Graph Jiro HAYAKAWA Shuji TSUKIYAMA Hiromu ARIYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 pp. 775-783 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: separating set, cutsets, mixed cutsets, enumeration, lowest common ancestor,
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On Improved FPGA Greedy Routing Architectures Yu-Liang WU Douglas CHANG Malgorzata MAREK-SADOWSKA Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2485-2491 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Optimization Keyword: FPGA architecture, FPGA Greedy routing architecture,
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A New Algorithm forp-Collection Problem on a Tree-Type Flow Network Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/01/25 Vol. E81-A No. 1 pp. 139-146 Type of Manuscript: PAPER Category: Graphs and Networks Keyword: flow network, location problem, p-collection problem, dynamic programming,
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FOREWORD Malgorzata MAREK-SADOWSKA Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 pp. 1689-1690 Type of Manuscript: FOREWORD Category: Keyword:
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A Hybrid Hierarchical Global Router for Multi-Layer VLSI's Masayuki HAYASHI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 pp. 337-344 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: hybrid hierarchical router, global routing, multi-layer routing, CAD, VLSI,
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FOREWORD Shuji TSUKIYAMA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/25 Vol. E76-A No. 3 pp. 257-258 Type of Manuscript: FOREWORD Category: Keyword:
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A Hierarchical Multi-Layer Global Router Masayuki HAYASHI Hiroyoshi YAMAZAKI Shuji TSUKIYAMA Nobuyuki NISHIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1294-1300 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: global router, layering, hierarchical router, multilayer VLSI, VLSI CAD,
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On an Algorithm to Detect Positive Cycles in a Constraint Graph for Layout Compaction Kunihiko ISHIMA Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/11/25 Vol. E74-A No. 11 pp. 3613-3616 Type of Manuscript: LETTER Category: Algorithms, Data Structures and Computational Complexity Keyword:
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A Consideration on a Sliding Palette Problem in a Two-Dimensional Automatic Warehouse Kenji SHIMIZU Akio SAKAMOTO Shuji TSUKIYAMA Mitsuru NUMATA Takashi KAWABATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/04/25 Vol. E74-A No. 4 pp. 644-652 Type of Manuscript: INVITED PAPER (Special Issue on Discrete Mathematics and Its Applications) Category: Keyword:
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On a Second Shortest k-Tuple of Edge-Disjoint Paths Shoji SHINODA Shuji TSUKIYAMA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/10/25 Vol. E70-E No. 10 pp. 945-950 Type of Manuscript: PAPER Category: Graphs and Networks Keyword:
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