Shuichi KANEDA

Boltzmann Machine Processor Using Single-Bit Operation
Mamoru SASAKI Shuichi KANEDA Fumio UENO Takahiro INOUE Yoshiki KITAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 878-885
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Nonlinear Circuits and Neural Nets
neural networkBoltzmann Machine multi processorsbus connection
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