IEICE Trans

Shuichi ICHIKAWA

Evaluation of Register Number Abstraction for Enhanced Instruction Register Files Naoki FUJIEDA Kiyohiro SATO Ryodai IWAMOTO Shuichi ICHIKAWA
Publication: Publication Date: 2018/06/01 Vol. E101-D No. 6 pp. 1521-1531 Type of Manuscript: PAPER Category: Computer System Keyword: computer architecture, embedded systems, instruction register files, secure processors,
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FPGA Implementation of Metastability-Based True Random Number Generator Hisashi HATA Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 426-436 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: TRNG, synchronous digital circuit, FPGA, entropy,
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FOREWORD Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/12/01 Vol. E94-D No. 12 pp. 2297-2297 Type of Manuscript: FOREWORD Category: Keyword:
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Diversification of Processors Based on Redundancy in Instruction Set Shuichi ICHIKAWA Takashi SAWADA Hisashi HATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 211-220 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: FPGA, embedded systems, instruction set, randomization, secure processor,
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Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm Ryoichiro ATONO Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/07/01 Vol. E89-D No. 7 pp. 2301-2305 Type of Manuscript: LETTER Category: VLSI Systems Keyword: FPGA, custom circuit, partial evaluation, specialization, cryptography, embedded system,
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Redundancy in Instruction Sequences of Computer Programs Kazuhiro HATTANDA Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/01/01 Vol. E89-A No. 1 pp. 219-221 Type of Manuscript: Special Section LETTER (Special Section on Cryptography and Information Security) Category: Information Hiding Keyword: information hiding, reordering, basic block, digital watermark,
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Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937 Shiro KONUMA Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/12/01 Vol. E88-D No. 12 pp. 2876-2879 Type of Manuscript: LETTER Category: VLSI Systems Keyword: custom circuit, simulation, random number, Mersenne Twister, FPGA,
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The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem Shoji YAMAMOTO Shuichi ICHIKAWA Hiroshi YAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2038-2047 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: FPGA, custom circuit, graph algorithm, NP-complete, partial evaluation,
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The Evaluation of Davidson's Digital Signature Scheme Kazuhiro HATTANDA Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/01/01 Vol. E87-A No. 1 pp. 224-225 Type of Manuscript: Special Section LETTER (Special Section on Cryptography and Information Security) Category: Keyword: digital signature, watermarking, computer program, basic block, permutation,
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Trade-Offs in Custom Circuit Designs for Subgraph Isomorphism Problems Shuichi ICHIKAWA Hidemitsu SAITO Lerdtanaseangtham UDORN Kouji KONISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/07/01 Vol. E86-D No. 7 pp. 1250-1257 Type of Manuscript: PAPER Category: VLSI Systems Keyword: NP-complete, graph, algorithm, FPGA,
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Data Dependent Circuit for Subgraph Isomorphism Problem Shuichi ICHIKAWA Shoji YAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 796-802 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: NP-complete, custom circuit, FPGA, graph algorithm,
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