Shuhei TANAKAMARU


Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths
Hirofumi TAKISHITA Shuhei TANAKAMARU Sheyang NING Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/04/01
Vol. E99-C  No. 4  pp. 444-451
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
solid-state drivestorage-class memoryNAND flash memoryerror correcting code
 Summary | Full Text:PDF

A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories
Shuhei TANAKAMARU Masafumi DOI Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/01/01
Vol. E98-C  No. 1  pp. 53-61
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
Error-correcting codeECClow-density parity-checkLDPCNAND flash memory
 Summary | Full Text:PDF

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor
Kousuke MIYAJI Kentaro HONDA Shuhei TANAKAMARU Shinji MIYANO Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 564-571
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
6T/8T-SRAMasymmetric pass gate transistorlocal electron injectiondisturb/write marginread speed
 Summary | Full Text:PDF