Shota ISHIHARA


Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates
Zhengfan XIA Shota ISHIHARA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/08/01
Vol. E95-C  No. 8  pp. 1434-1443
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
asynchronous pipelinedual-railcritical datapath
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Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/10/01
Vol. E94-C  No. 10  pp. 1669-1679
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
mixed synchronous/asynchronous designreconfigurable VLSIfour-phase dual-rail encodingself-timed architectureGALS (Globally Asynchronous Locally Synchronous)
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An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1338-1348
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
reconfigurable VLSIfield-programmable VLSILEDR (Level-Encoded Dual-Rail) encoding4-phase dual-rail encodingself-timed architecture
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A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
Shota ISHIHARA Noriaki IDOBATA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2134-2144
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
Keyword: 
dynamically programmable gate arraymulti-context switchlogic-in-memory circuitmultiple-valued threshold logicnonvolatile storagenon-destructive operation
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Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1419-1426
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAsreconfigurable VLSIsasynchronous architectureLEDR (Level-Encoded Dual-Rail) encoding
 Summary | Full Text:PDF