Shinya TAKAMAEDA-YAMAZAKI

FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho YAMAMOTO Masayuki IKEBE Tetsuya ASAI Masato MOTOMURA Shinya TAKAMAEDA-YAMAZAKI 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2295-2305
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
ising model, annealing processor, simulated annealing, 
 Summary | Full Text:PDF
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
Kota ANDO Kodai UEYOSHI Yuka OBA Kazutoshi HIROSE Ryota UEMATSU Takumi KUDO Masayuki IKEBE Tetsuya ASAI Shinya TAKAMAEDA-YAMAZAKI Masato MOTOMURA 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2341-2353
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
neural network, dithering, error diffusion, FPGA, hardware-oriented neural network algorithm, 
 Summary | Full Text:PDF
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing
Hoang-Gia VU Shinya TAKAMAEDA-YAMAZAKI Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 288-302
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
Keyword: 
checkpointing, FPGA, dependability, tree-based, 
 Summary | Full Text:PDF
Performance Optimization of Light-Field Applications on GPU
Yuttakon YUTTAKONKIT Shinya TAKAMAEDA-YAMAZAKI Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 3072-3081
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
light-field image processing, GPU optimization, GPU architecture, 
 Summary | Full Text:PDF
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators
Yoshikazu INAGAKI Shinya TAKAMAEDA-YAMAZAKI Jun YAO Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12  pp. 2141-2149
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
CGRA, coarse grained reconfigurable architecture, accelerator, library, stencil, optimization, 
 Summary | Full Text:PDF
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
Shinya TAKAMAEDA-YAMAZAKI Hiroshi NAKATSUKA Yuichiro TANAKA Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12  pp. 2150-2158
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
soft processor, processor architecture, FPGA, 
 Summary | Full Text:PDF