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A 1.2 V, 30 MIPS, 0.3 mA/MIPS and 200 MIPS, 0.58 mA/MIPS Digital Signal Processors Hiroshi TAKAHASHI Shintaro MIZUSHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C
No. 2
pp. 179-185
Type of Manuscript:
Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: high speed, super low power, MIPS, fixed point DSP, pocket implant, D flip-flop, VIA-2 ROM, 1.2 V, 200 MIPS, | | Summary | Full Text:PDF | |
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A Circuit Library for Low Power and High Speed Digital Signal Processor Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C
No. 12
pp. 1717-1725
Type of Manuscript:
Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: low power, high speed, low cost, GSM, PDC, NADC, digital signal processing, personal communication, 50 MIPS, CPU, | | Summary | Full Text:PDF | |
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