| Shinobu MIWA
|
|
|
|
|
|
|
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2301-2308
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: low-power, cache, leakage power, | | Summary | Full Text:PDF | |
|
|
|
|
|
|