IEICE Trans

Shinji MIYANO

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress Toshiro HIRAMOTO Anil KUMAR Takuya SARAYA Shinji MIYANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 759-765 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: transistor, MOSFET, variability, off-state stress,
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NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM Nurul Ezaila ALIAS Anil KUMAR Takuya SARAYA Shinji MIYANO Toshiro HIRAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/05/01 Vol. E96-C No. 5 pp. 620-623 Type of Manuscript: BRIEF PAPER Category: Keyword: Negative Bias Temperature Instability (NBTI), variability, SRAM, transistor, MOSFET,
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A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke YOSHIMOTO Masaharu TERADA Shunsuke OKUMURA Toshikazu SUZUKI Shinji MIYANO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 572-578 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, 8T, low energy, disturb, half select, write back,
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Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor Kousuke MIYAJI Kentaro HONDA Shuhei TANAKAMARU Shinji MIYANO Ken TAKEUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 564-571 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: 6T/8T-SRAM, asymmetric pass gate transistor, local electron injection, disturb/write margin, read speed,
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