Shinichiro SHIRATAKE


Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI
Yukihito OOWAKI Shinichiro SHIRATAKE Toshihide FUJIYOSHI Mototsugu HAMADA Fumitoshi HATORI Masami MURAKATA Masafumi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 263-270
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
dynamic voltage/frequency scalingsystem LSIH.264MPEG-4A/V codec LSImultimedia chip
 Summary | Full Text:PDF

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
 Summary | Full Text:PDF