Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A
No. 12
pp. 3208-3210
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword:
delay testing, path delay fault, path selection, untestable path, |
