Shinichi NISHIZAWA

Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells
Yuki IMAI Shinichi NISHIZAWA Kazuhito ITO 
Publication:   
Publication Date: 2022/03/01
Vol. E105-A  No. 3  pp. 487-496
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
maximum power reduction, low speed operation, standard cell, stack structure, 
 Summary | Full Text:PDF
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis
Shinichi NISHIZAWA Hidetoshi ONODERA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2222-2230
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
D-Flip-Flop, variation aware design, regression analysis, 
 Summary | Full Text:PDF
Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution
Kazuhito ITO Yuto ISHIHARA Shinichi NISHIZAWA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2271-2279
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
soft error, error detection, DMR, checkpoint, scheduling, 
 Summary | Full Text:PDF
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation
Shinichi NISHIZAWA Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2499-2507
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
standard cell design, low power circuit design, near threshold operation, PN ratio optimization, 
 Summary | Full Text:PDF