Shinichi MARUI


An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital Signal Processor
Hideyuki KABUO Minoru OKAMOTO Isao TANAKA Hiroyuki YASOSHIMA Shinichi MARUI Masayuki YAMASAKI Toshio SUGIMURA Katsuhiko UEDA Toshihiro ISHIKAWA Hidetoshi SUZUKI Ryuichi ASAHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 905-914
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Logic
Keyword: 
 Summary | Full Text:PDF

A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption
Katsuhiko UEDA Toshio SUGIMURA Toshihiro ISHIKAWA Minoru OKAMOTO Mikio SAKAKIHARA Shinichi MARUI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12  pp. 1709-1716
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
integrated electronicsdigital signal processorlow power consumptioncommunication
 Summary | Full Text:PDF