Shigeto TANAKA

A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture
Hiroki SAKURAI Shigeto TANAKA Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/10/01
Vol. E90-A  No. 10  pp. 2272-2279
Type of Manuscript:  PAPER
Category: Analog Signal Processing
capacitor mismatchCMOS pipelined ADC1.5-bit bit-blocksaveraging in digital domainOversampling ADC
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A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications
Yasuhiro SUGIMOTO Yuji GOHDA Shigeto TANAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6  pp. 811-813
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
current-mode circuitpipelined ADClow-voltagehigh-resolution
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