Shigetaka KUMASHIRO


Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
Satoshi TAKAYA Yoji BANDO Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6  pp. 884-893
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
mixed signal VLSI circuitsubstrate crosstalkon-chip noise monitoring
 Summary | Full Text:PDF(3MB)

On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors
Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/01/01
Vol. E95-C  No. 1  pp. 137-145
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
on-chip monitorsubstrate noisedifferential amplifier
 Summary | Full Text:PDF(2.1MB)

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
Masaaki SODA Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1024-1031
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
noisesine waveharmonic
 Summary | Full Text:PDF(1.7MB)

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 495-503
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
on-chip monitorpower supply noise
 Summary | Full Text:PDF(2.4MB)

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1349-1358
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STIstressmodelverificationenhancement
 Summary | Full Text:PDF(2.2MB)

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
Kenta YAMADA Takashi SATO Shuhei AMAKAWA Noriaki NAKAYAMA Kazuya MASU Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/07/01
Vol. E91-C  No. 7  pp. 1142-1150
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STIstressmodelingSPICElayout-aware
 Summary | Full Text:PDF(1.3MB)

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential
Dondee NAVARRO Takeshi MIZOGUCHI Masami SUETAKE Kazuya HISAMITSU Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 1079-1086
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
pinch-off regionchannel-length modulationoverlap capacitancesurface-potential-based modelingcircuit simulation
 Summary | Full Text:PDF(1MB)

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation
Shizunori MATSUMOTO Hiroaki UENO Satoshi HOSOKAWA Toshihiko KITAMURA Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Tatsuya OHGURO Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/02/01
Vol. E88-C  No. 2  pp. 247-254
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
100 nm-MOSFET1/f noisemeasurementmodeling
 Summary | Full Text:PDF(438.8KB)

Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients
Dondee NAVARRO Hiroaki KAWANO Kazuya HISAMITSU Takatoshi YAMAOKA Masayasu TANAKA Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 474-480
Type of Manuscript:  INVITED PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
gate-drain capacitancesurface-potential based modelinglateral field gradientpocket-implant technology
 Summary | Full Text:PDF(1MB)

Circuit Simulation Models for Coming MOSFET Generations
Mitiko MIURA-MATTAUSCH Hiroaki UENO Hans Juergen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 740-748
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
MOSFET modelsurface potentialcharge based modelingsub-100 nm technology
 Summary | Full Text:PDF(483.7KB)

Advanced Process/Device Modeling and Its Impact on the CMOS Design Solution
Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/08/25
Vol. E83-C  No. 8  pp. 1281-1287
Type of Manuscript:  INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Simulation Methodology and Environment
Keyword: 
process modelingdevice modeling0.13 [µm] CMOS
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Modeling of Channel Boron Distribution in Deep Sub-0.1 µm n-MOSFETs
Shigetaka KUMASHIRO Hironori SAKAMOTO Kiyoshi TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 813-820
Type of Manuscript:  Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
deep sub-0.1 [µm] n-MOSFETreverse short channel effectpoint-defect pair diffusion modelinverse modeling
 Summary | Full Text:PDF(745.8KB)

Efficient Transient Device Simulation with AWE Macromodels and Domain Decomposition
Howard C. READ Shigetaka KUMASHIRO Andrzej STROJWAS 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 236-247
Type of Manuscript:  Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))
Category: Numerics
Keyword: 
semiconductor materials and devices
 Summary | Full Text:PDF(961.2KB)