|
| Shigeshi ABIKO
|
A 1.5 V, 200 MHz, 400 MIPS, 188 µA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169 µA/MHz Digital Signal Processor Core for 3G Wireless Applications
Hiroshi TAKAHASHI Shigeshi ABIKO Kenichi TASHIRO Kaoru AWAKA Yutaka TOYONOH Rimon IKENO Shigetoshi MURAMATSU Yasumasa IKEZAKI Tsuyoshi TANAKA Akihiro TAKEGAMA Hiroshi KIMIZUKA Hidehiko NITTA Miki KOJIMA Masaharu SUZUKI James Lowell LARIMER | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4
pp. 491-501
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
200 MHz, 300 MHz, 400 MIPS, 600 MIPS, high-speed, low-power, fixed point DSP, 130 nm, | | | Summary | Full Text:PDF | |
| |
|
|
A Circuit Library for Low Power and High Speed Digital Signal Processor
Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C
No. 12
pp. 1717-1725
Type of Manuscript:
Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category:
Keyword:
low power, high speed, low cost, GSM, PDC, NADC, digital signal processing, personal communication, 50 MIPS, CPU, | | | Summary | Full Text:PDF | |
|
|
