IEICE Trans

Shigeru YAMASHITA

Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation Yudai SAKAMOTO Shigeru YAMASHITA
Publication: Publication Date: 2020/02/01 Vol. E103-D No. 2 pp. 321-328 Type of Manuscript: PAPER Category: Computer System Keyword: Stochastic Computing, Stochastic Number, correlation,
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Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order Wakaki HATTORI Shigeru YAMASHITA
Publication: Publication Date: 2019/11/01 Vol. E102-D No. 11 pp. 2127-2134 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: Nearest Neighbor Architecture (NNA), gate order,
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Compaction of Topological Quantum Circuits by Modularization Kota ASAI Shigeru YAMASHITA
Publication: Publication Date: 2019/04/01 Vol. E102-A No. 4 pp. 624-632 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: topological quantum computation, qubit layout, circuit optimization, simulated annealing,
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Stochastic Number Generation with the Minimum Inputs Ritsuko MUGURUMA Shigeru YAMASHITA
Publication: Publication Date: 2017/08/01 Vol. E100-A No. 8 pp. 1661-1671 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: stochastic computing, stochastic number generation, minimum number of inputs,
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Reduction of Quantum Cost by Making Temporary Changes to the Function Nurul AIN BINTI ADNAN Shigeru YAMASHITA Alan MISHCHENKO
Publication: Publication Date: 2017/07/01 Vol. E100-D No. 7 pp. 1393-1402 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: quantum cost, changing functionality, Mixed Polarity Multiple Control Toffoli gates, ESOP,
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A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers Takahiro YAMAMOTO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Shigeru YAMASHITA Yuko HARA-AZUMI
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1496-1499 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: approximate computing, array multipliers, SMT solver,
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A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips Trung Anh DINH Shigeru YAMASHITA Tsung-Yi HO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/02/01 Vol. E99-A No. 2 pp. 570-578 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: digital microfluidic biochips, combinational logic, pin-count reduction, general purpose,
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An Energy-Efficient Patchable Accelerator and Its Design Methods Hiroaki YOSHIDA Masayuki WAKIZAKA Shigeru YAMASHITA Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2507-2517 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: engineering change, high-level synthesis, energy efficiency,
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Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips Trung Anh DINH Shigeru YAMASHITA Tsung-Yi HO Yuko HARA-AZUMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2668-2679 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: flow-based microfluidic biochip, architectural synthesis, binding, scheduling, clique,
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Selective Check of Data-Path for Effective Fault Tolerance Tanvir AHMED Jun YAO Yuko HARA-AZUMI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1592-1601 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: low power, fault-tolerant computing, FU array,
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Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/01/01 Vol. E96-D No. 1 pp. 1-8 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: multiparty communication complexity, quantum computation, quantum nondeterminism, tensor rank,
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Quantum Walks on the Line with Phase Parameters Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/03/01 Vol. E95-D No. 3 pp. 722-730 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science – Mathematical Foundations and Applications of Computer Science and Algorithms –) Category: Keyword: quantum computation, random walks, quantum walks, asymptotic approximation,
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Multi-Party Quantum Communication Complexity with Routed Messages Seiichiro TANI Masaki NAKANISHI Shigeru YAMASHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 191-199 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Keyword: quantum communication complexity, network topology, distributed computing,
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DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3793-3802 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: quantum circuit, verification, decision diagram,
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Robust Quantum Algorithms Computing OR with ε-Biased Oracles Tomoya SUZUKI Shigeru YAMASHITA Masaki NAKANISHI Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/02/01 Vol. E90-D No. 2 pp. 395-402 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Quantum Computing Keyword: quantum computing, biased oracle, phase estimation,
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An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs Mitsuru TOMONO Masaki NAKANISHI Shigeru YAMASHITA Kazuo NAKAJIMA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3416-3426 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: algorithm, online placement, partially reconfigurable FPGAs, reconfigurable computing,
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SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits Katsunori TANAKA Shigeru YAMASHITA Yahiko KAMBAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 1038-1046 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic design, set of pairs of functions to be distinguished (SPFD), look-up-table-based (LUT-based) field programmable gate array (FPGA), SPFD-based effective wire addition,
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Quantum Sampling for Balanced Allocations Kazuo IWAMA Akinori KAWACHI Shigeru YAMASHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/01/01 Vol. E88-D No. 1 pp. 39-46 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science) Category: Keyword: quantum computing, load balancing, balls-and-bins game,
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A General Framework to Use Various Decomposition Methods for LUT Network Synthesis Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2915-2922 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: functional decomposition, algebraic decomposition, field programmable gate array (FPGA), look-up table (LUT),
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Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2513-2519 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: multi-level logic synthesis, sum-of-products expression, implicit cube set representation, kernel,
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Restructuring Logic Representations with Simple Disjunctive Decompositions Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2538-2544 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: simple disjunctive decomposition, symmetric variables, ordered binary decision diagram, multi-level logic circuit,
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Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2554-2562 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic optimization, FPGAs, SPFDs, PSPFDs,
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An Efficient Method for Finding an Optimal Bi-Decomposition Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2529-2537 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: functional decomposition, bi-decomposition, AND, XOR, look-up table,
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