IEICE Trans

Shigeo SATO

Learning Rule for a Quantum Neural Network Inspired by Hebbian Learning Yoshihiro OSAKABE Shigeo SATO Hisanao AKIMA Mitsunaga KINJO Masao SAKURABA
Publication: Publication Date: 2021/02/01 Vol. E104-D No. 2 pp. 237-245 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: learning, quantum neural network, Hebb rule, Boltzmann machine, adiabatic quantum computation,
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Quantum Associative Memory with Quantum Neural Network via Adiabatic Hamiltonian Evolution Yoshihiro OSAKABE Hisanao AKIMA Masao SAKURABA Mitsunaga KINJO Shigeo SATO
Publication: Publication Date: 2017/11/01 Vol. E100-D No. 11 pp. 2683-2689 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: associative memory, quantum computing, adiabatic Hamiltonian evolution, neural network,
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CMOS Majority Circuit with Large Fan-In Hisanao AKIMA Yasuhiro KATAYAMA Masao SAKURABA Koji NAKAJIMA Jordi MADRENAS Shigeo SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/09/01 Vol. E99-C No. 9 pp. 1056-1064 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: majority logic, MOS analog circuits, nonlinear circuits, Monte Carlo simulation,
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High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform Ryosuke NAKAMOTO Sakae SAKURABA Alexandre MARTINS Takeshi ONOMI Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/03/01 Vol. E94-C No. 3 pp. 280-287 Type of Manuscript: Special Section PAPER (Special Section on Superconducting Signal Processing Technologies) Category: Keyword: SFQ, super-conductive circuits, FFT, multiplier, adder,
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Macroscopic Quantum Tunneling and Resonant Activation of Current Biased Intrinsic Josephson Junctions in Bi-2212 Shigeo SATO Kunihiro INOMATA Mitsunaga KINJO Nobuhiro KITABATAKE Koji NAKAJIMA Huabing WANG Takeshi HATANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/03/01 Vol. E90-C No. 3 pp. 599-604 Type of Manuscript: INVITED PAPER (Special Section on Innovative Superconducting Devices and Their Applications) Category: Keyword: Josephson junction, macroscopic quantum tunneling, high-Tc superconductor, resonant activation, qubit,
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Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic Hongge LI Yoshihiro HAYAKAWA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/09/01 Vol. E89-D No. 9 pp. 2572-2578 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: inverse function delayed model, associative memory, field programmable gate array (FPGA), stochastic logic,
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Implementation of Continuous-Time Dynamics on Stochastic Neurochip Shunsuke AKIMOTO Akiyoshi MOMOI Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/09/01 Vol. E87-A No. 9 pp. 2227-2232 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: stochastic logic, nonmonotonic neuron, continuous-time dynamics, asynchronous updating, associative memories, traveling salesman problem, large scale integration (LSI) implementation,
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Single Electron Stochastic Neural Network Hisanao AKIMA Saiboku YAMADA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/09/01 Vol. E87-A No. 9 pp. 2221-2226 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: single electron transistor (SET), artificial neural network (ANN), stochastic logic, single electron random number generator,
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Single Electron Random Number Generator Hisanao AKIMA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/05/01 Vol. E87-C No. 5 pp. 832-834 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: random number generator, single electron transistor, Monte Carlo simulation,
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Hardware Implementation of a DBM Network with Non-monotonic Neurons Mitsunaga KINJO Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/03/01 Vol. E85-D No. 3 pp. 558-567 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: neural network, non-monotonic, DBM learning, analog circuit, neurochip,
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A Content-Addressable Memory Using "Switched Diffusion Analog Memory with Feedback Circuit" Tomochika HARADA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 370-377 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: nonvolatile analog memory, content-addressable memory, recognition, SDAM, analog technology,
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Integrated Circuits of Map Chaos Generators Hidetoshi TANAKA Shigeo SATO Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 364-369 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: chaotic noise, map chaos, integrated circuit, Lyapunov exponent, neural network,
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Theoretical Study of Alpha-Particle-lnduced Soft Errors in Submicron SOI SRAM Yoshiharu TOSAKA Kunihiro SUZUKI Shigeo SATOH Toshihiro SUGII
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 767-771 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: soft errors, SOI SRAM, α-particle-induced bipolar current, critical α-particle-induced initial charge, soft error rate,
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LSI Neural Chip of Pulse-Output Network with Programmable Synapse Shigeo SATO Manabu YUMINE Takayuki YAMA Junichi MUROTA Koji NAKAJIMA Yasuji SAWADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/01/25 Vol. E78-C No. 1 pp. 94-100 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: neurochip, pulse, analog, programmable synapse,
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Hardware Implementation of New Analog Memory for Neural Networks Koji NAKAJIMA Shigeo SATO Tomoyasu KITAURA Junichi MUROTA Yasuji SAWADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/01/25 Vol. E78-C No. 1 pp. 101-105 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: analog memory, floating gate, neurochip, SDAM,
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