Shigeo OHSHIMA


High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1303-1315
Type of Manuscript:  INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMmemory bottleneckdata bandwidthlatencysynchronous DRAMpipeline architecturedata prefetchingcache DRAMfast copybackRambus interfaceRambus DRAMprotocol packetPLL
 Summary | Full Text:PDF

A 500-Megabyte/s Data-Rate 4.5M DRAM
Natsuki KUSHIYAMA Shigeo OHSHIMA Don STARK Hiroyuki NOJI Kiyofumi SAKURAI Satoru TAKASE Tohru FURUYAMA Richard M. BARTH Andy CHAN John DILLON James A. GASBARRO Matthew M. GRIFFIN Mark HOROWITZ Thomas H. LEE Victor LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 830-838
Type of Manuscript:  Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
 Summary | Full Text:PDF