Shigeo KUNINOBU


Layout Abstraction and Technology Retargeting for Leaf Cells
Masahiro FUKUI Noriko SHINOMIYA Syunji SAIKA Toshiro AKINO Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2492-2500
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
technology retargetinglayout abstractionlayout synthesiscell synthesis
 Summary | Full Text:PDF(906.1KB)

Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops
Toshinori HOSOKAWA Toshihiro HIRAOKA Mitsuyasu OHTA Michiaki MURAOKA Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 660-667
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
design for testabilitypartial scan design methodn-fold line-up structurepure load/hold FF
 Summary | Full Text:PDF(715.5KB)

A Two-Dimensional Transistor Placement Algorithm for Cell Synthesis and Its Application to Standard Cells
Shunji SAIKA Masahiro FUKUI Noriko SHINOMIYA Toshiro AKINO Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1883-1891
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
cell layoutcell synthesistransistor placementtwo-dimensional placement
 Summary | Full Text:PDF(940.3KB)

High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor
Shigeo KUNINOBU Tamotsu NISHIYAMA Takashi TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 436-445
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiplierdividerredundant binarymicroprocessor
 Summary | Full Text:PDF(852.9KB)

The Performance Evaluation of a 64 b Microprocessor with a Two-Level Cache
Ryuichi YAMAGUCHI Joel BONEY Douglas DUSCHATKO Tetsuya TANAKA Jiro MIYAKE Yoshito NISHIMICHI Hisakazu EDAMATSU Shigeru WATARI Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3803-3809
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: System VLSI
Keyword: 
 Summary | Full Text:PDF(681.4KB)