Sheqin DONG


Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System
Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2208-2219
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dual-vddmin-cutvoltage assignmentlow powertiming constraints
 Summary | Full Text:PDF

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips
Wei ZHONG Takeshi YOSHIMURA Bei YU Song CHEN Sheqin DONG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 534-545
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
networks on chip (NoC)placementsynthesistopology
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Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs
Kan WANG Sheqin DONG Yuchun MA Yu WANG Xianlong HONG Jason CONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2490-2498
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
leakage powerTSVdelay-power-temperature dependence
 Summary | Full Text:PDF

Voltage and Level-Shifter Assignment Driven Floorplanning
Bei YU Sheqin DONG Song CHEN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 2990-2997
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Desing
Keyword: 
voltage-islandvoltage assignmentconvex network flowlevel shifter assignmentwhite space redistribution
 Summary | Full Text:PDF

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis
Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2283-2294
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
application partitioningCAD algorithmMPSoCASIPsynthesis
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Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System
Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9  pp. 2456-2464
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Electronic Circuits and Systems
Keyword: 
hardware/software partitioningCAD algorithmsearch space smoothingMPSoCASIP
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Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design
Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/06/01
Vol. E91-A  No. 6  pp. 1478-1487
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
custom instruction identificationbasic convex pattern (BCP)system-on-a-chip (SoC)application specific instruction-set processor (ASIP)
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VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing
Sheqin DONG Xianlong HONG Song CHEN Xin QI Ruijie WANG Jun GU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3136-3147
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Place and Routing
Keyword: 
floorplanplacementsolution space smoothing
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VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2697-2704
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
floorplancorner block listsimulated annealingboundary constraints
 Summary | Full Text:PDF