Sheng-Yu HSU


Opposite-Phase Clock Tree for Peak Current Reduction
Yow-Tyng NIEH Shih-Hsu HUANG Sheng-Yu HSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2727-2735
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
clocksdesign methodologydigital circuits
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