Sheldon X.-D. TAN


Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method
Duo LI Sheldon X.-D. TAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3061-3069
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power grid analysismodel order reductiontruncated balanced realization
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A Fast Delay Computation for the Hybrid Structured Clock Network
Yi ZOU Yici CAI Qiang ZHOU Xianlong HONG Sheldon X.-D. TAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7  pp. 1964-1970
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock networkssimulationanalysisdelayElmore delay
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A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Chip Power Delivery
Jingjing FU Zuying LUO Xianlong HONG Yici CAI Sheldon X.-D. TAN Zhu PAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3273-3280
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
power deliveryoptimizationdecoupling capacitornon-linear programming
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Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits
Sheldon X.-D. TAN C.-J. Richard SHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3110-3118
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Design
Keyword: 
circuit simulationbehavioral modelingsymbolic analysisdeterminant decision diagrams
 Summary | Full Text:PDF