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Copyright (c) by IEICE
Setsuo WAKE
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros
Akira YAMAZAKI
Fukashi MORISHITA
Naoya WATANABE
Teruhiko AMANO
Masaru HARAGUCHI
Hideyuki NODA
Atsushi HACHISUKA
Katsumi DOSAKA
Kazutami ARIMOTO
Setsuo WAKE
Hideyuki OZAKI
Tsutomu YOSHIHARA
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2005/10/01
Vol.
E88-C
No.
10
pp.
2020-2027
Type of Manuscript:
PAPER
Category:
Integrated Electronics
Keyword:
embedded memory
,
DRAM
,
voltage margin
,
low voltage
,
system on chip
,
Summary
|
Full Text:PDF
A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Akira YAMAZAKI
Takeshi FUJINO
Kazunari INOUE
Isamu HAYASHI
Hideyuki NODA
Naoya WATANABE
Fukashi MORISHITA
Katsumi DOSAKA
Yoshikazu MOROOKA
Shinya SOEDA
Kazutami ARIMOTO
Setsuo WAKE
Kazuyasu FUJISHIMA
Hideyuki OZAKI
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2002/09/01
Vol.
E85-C
No.
9
pp.
1697-1708
Type of Manuscript:
PAPER
Category:
Electronic Circuits
Keyword:
embedded DRAM
,
system on chip
,
3-D graphics concurrent operation
,
Summary
|
Full Text:PDF