Sergio SAPONARA

Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
Sergio SAPONARA Pierluigi NUZZO Claudio NANI Geert VAN DER PLAS Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 843-851
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/D converters, time interleaving, analog CMOS circuits, system level design, SAR, low power design, 
 Summary | Full Text:PDF
Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
Nicola E. L'INSALATA Sergio SAPONARA Luca FANUCCI Pierangelo TERRENI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 487-496
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
FFT, OFDM communication system, configurable macrocell, IP reuse, 
 Summary | Full Text:PDF
Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems
Luca FANUCCI Sergio SAPONARA Massimiliano MELANI Pierangelo TERRENI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1538-1545
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Adaptive Signal Processing
Keyword: 
adaptive signal processing, low-power, VLSI architectures, image processing and multimedia systems, H.264, 
 Summary | Full Text:PDF
Power Optimization of an 8051-Compliant IP Microcontroller
Luca FANUCCI Sergio SAPONARA Alexander MORELLO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 597-600
Type of Manuscript:  Special Section LETTER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
low-power, VLSI, intellectual property (IP) cells, 8051 microcontroller, 
 Summary | Full Text:PDF
Data Driven Power Saving for DCT/IDCT VLSI Macrocell
Luca FANUCCI Sergio SAPONARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7  pp. 1760-1765
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
very large scale integration architectures, low power design, design reuse, clock gating, video coding, 
 Summary | Full Text:PDF