Sergio SAPONARA


Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
Sergio SAPONARA Pierluigi NUZZO Claudio NANI Geert VAN DER PLAS Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 843-851
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/D converterstime interleavinganalog CMOS circuitssystem level designSARlow power design
 Summary | Full Text:PDF(921.8KB)

Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
Nicola E. L'INSALATA Sergio SAPONARA Luca FANUCCI Pierangelo TERRENI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 487-496
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
FFTOFDM communication systemconfigurable macrocellIP reuse
 Summary | Full Text:PDF(557.1KB)

Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems
Luca FANUCCI Sergio SAPONARA Massimiliano MELANI Pierangelo TERRENI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1538-1545
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Adaptive Signal Processing
Keyword: 
adaptive signal processinglow-powerVLSI architecturesimage processing and multimedia systemsH.264
 Summary | Full Text:PDF(529.4KB)

Power Optimization of an 8051-Compliant IP Microcontroller
Luca FANUCCI Sergio SAPONARA Alexander MORELLO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 597-600
Type of Manuscript:  Special Section LETTER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
low-powerVLSIintellectual property (IP) cells8051 microcontroller
 Summary | Full Text:PDF(184.8KB)

Data Driven Power Saving for DCT/IDCT VLSI Macrocell
Luca FANUCCI Sergio SAPONARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7  pp. 1760-1765
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
very large scale integration architectureslow power designdesign reuseclock gatingvideo coding
 Summary | Full Text:PDF(466.8KB)