Seongjae CHO


Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell
Sungjun KIM Min-Hwi KIM Seongjae CHO Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/05/01
Vol. E99-C  No. 5  pp. 547-550
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
resistive random-access memory (RRAM)silicon nitride (Si3N4)bias polarityswitching parameters
 Summary | Full Text:PDF

Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals
Sungjun KIM Sunghun JUNG Min-Hwi KIM Seongjae CHO Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/05/01
Vol. E98-C  No. 5  pp. 429-433
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
RRAMswitching and conduction mechanismtop electrode (TE)
 Summary | Full Text:PDF

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate
Sung YUN WOO Young JUN YOON Jae HWA SEO Gwan MIN YOO Seongjae CHO In MAN KANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/07/01
Vol. E97-C  No. 7  pp. 677-682
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Simulation Techniques and Their Applications for Electronics)
Category: 
Keyword: 
InGaAs/Si heterojunctiongate-all-around (GAA)tunneling field-effect transistor (TFET)and tunneling-boost n-layer
 Summary | Full Text:PDF

A New 1T DRAM Cell: Cone Type 1T DRAM Cell
Gil Sung LEE Doo-Hyun KIM Seongjae CHO Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5  pp. 681-685
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
1T DRAMconeelectric field concentration
 Summary | Full Text:PDF

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Seongjae CHO Jung Hoon LEE Yoon KIM Jang-Gn YUN Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 596-601
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Flash/Advanced Memory
Keyword: 
NANDflash memoryprogram inhibitionself-boostingFinFETdevice simulation
 Summary | Full Text:PDF

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
Dong Seup LEE Hong-Seon YANG Kwon-Chil KANG Joung-Eob LEE Jung Han LEE Seongjae CHO Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 540-545
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Multi-Gate Technology
Keyword: 
tunnel field-effect transistorsubthreshold swing
 Summary | Full Text:PDF

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Seongjae CHO Jung Hoon LEE Gil Sung LEE Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 620-626
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
3-D nonvolatile memoryNAND flash memory arraysaturation currentchannel potential barriergate-induced barrier lowering (GIBL)
 Summary | Full Text:PDF

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Yoon KIM Seongjae CHO Gil Sung LEE Il Han PARK Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 653-658
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
NANDflash memorystacked NANDvertical channel
 Summary | Full Text:PDF

Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
Sang Hyuk PARK Sangwoo KANG Seongjae CHO Dong-Seup LEE Jung Han LEE Hong-Seon YANG Kwon-Chil KANG Joung-Eob LEE Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 647-652
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
single electron transistorrecessed channelMOSFET current suppression
 Summary | Full Text:PDF

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
Doo-Hyun KIM Il Han PARK Seongjae CHO Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 659-663
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
SONOSflash memorynitride-based charge trap memoryretentionmulti-bitdouble gate
 Summary | Full Text:PDF

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Seongjae CHO Il Han PARK Jung Hoon LEE Jang-Gn YUN Doo-Hyun KIM Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 731-735
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
memory arrayelectrical interference3-D memory deviceread operationPCI (paired cell interference)
 Summary | Full Text:PDF

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Jang Gn YUN Il Han PARK Seongjae CHO Jung Hoon LEE Doo-Hyun KIM Gil Sung LEE Yoon KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 742-746
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
2-bit recessed channel memorylifted-charge trapping node (L-CTN) schemeshort channel effect (SCE)second bit effect (SBE)bottom-side effect (BSE)VTH window
 Summary | Full Text:PDF

Design and Simulation of Asymmetric MOSFETs
Jong Pil KIM Woo Young CHOI Jae Young SONG Seongjae CHO Sang Wan KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 978-982
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Junction Formation and TFT Reliability
Keyword: 
asymmetric MOSFETLDDmesa structuresidewall spacer gate
 Summary | Full Text:PDF

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices
Seongjae CHO Jang-Gn YUN Il Han PARK Jung Hoon LEE Jong Pil KIM Jong-Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 988-993
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Novel MOSFET Structures
Keyword: 
3-D devicesvertical ion implantationdoping profileconcentration peakdoping gradient
 Summary | Full Text:PDF

Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs
Hochul LEE Youngchang YOON Seongjae CHO Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 968-972
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Ultra-Thin Gate Insulators
Keyword: 
trap depthRTNtime constantspoly gate depletion effectsurface potential variation
 Summary | Full Text:PDF