Seiya KASAI


Analysis on Non-Ideal Nonlinear Characteristics of Graphene-Based Three-Branch Nano-Junction Device
Xiang YIN Masaki SATO Seiya KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/05/01
Vol. E98-C  No. 5  pp. 434-438
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
grapheneTBJnonlinear characteristiccontact resistancegraphene-metal contact
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Fabrication and Characterization of Active and Sequential Circuits Utilizing Schottky-Wrap-Gate-Controlled GaAs Hexagonal Nanowire Network Structures
Hong-Quan ZHAO Seiya KASAI Tamotsu HASHIZUME Nan-Jian WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/07/01
Vol. E91-C  No. 7  pp. 1063-1069
Type of Manuscript:  Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2007)
Category: Emerging Devices
Keyword: 
Schottky wrap gate (WPG)GaAs hexagonal nanowire networkflip flop (FF)ring oscillator
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Future of Heterostructure Microelectronics and Roles of Materials Research for Its Progress
Hideki HASEGAWA Seiya KASAI Taketomo SATO Tamotsu HASHIZUME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/07/01
Vol. E89-C  No. 7  pp. 874-882
Type of Manuscript:  INVITED PAPER (Special Section on Heterostructure Microelectronics with TWHM2005)
Category: 
Keyword: 
heterostructureIII-V semiconductorsnanotechnologyhigh speed devicessensorssmart chips
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Hexagonal Binary Decision Diagram Quantum Circuit Approach for Ultra-Low Power III-V Quantum LSIs
Hideki HASEGAWA Seiya KASAI Taketomo SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1757-1768
Type of Manuscript:  INVITED PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
quantum LSIquantum devicesbinary decision diagram (BDD)nanostructure networkintelligent quantum (IQ) chip
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Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HEMTs Having a Silicon Interface Control Layer
Yong-Gui XIE Seiya KASAI Hiroshi TAKAHASHI Chao JIANG Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1335-1343
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
insulated gatePHEMTInGaAsinterface controlFermi level pinning
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Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer
Hiroshi TAKAHASHI Masatsugu YAMADA Yong-Gui XIE Seiya KASAI Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1344-1349
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
InPMISFETXPSC-V
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