IEICE Trans

Seiji KAJIHARA

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Fuqiang LI Xiaoqing WEN Kohei MIYASE Stefan HOLST Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2310-2319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: at-speed scan testing, IR-drop, capture-power-safety, logic path, clock path, clock stretch, test quality,
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On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST Akihiro TOMITA Xiaoqing WEN Yasuo SATO Seiji KAJIHARA Kohei MIYASE Stefan HOLST Patrick GIRARD Mohammad TEHRANIPOOR Laung-Terng WANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/10/01 Vol. E97-D No. 10 pp. 2706-2718 Type of Manuscript: PAPER Category: Dependable Computing Keyword: at-speed scan-based logic BIST, capture power safety, masking, IR-drop, transition delay fault, long sensitized path,
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A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing Kohei MIYASE Ryota SAKAI Xiaoqing WEN Masao ASO Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 2003-2011 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: at-speed testing, ATPG, IR-drop, test power reduction, low power test,
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Scan-Out Power Reduction for Logic BIST Senling WANG Yasuo SATO Seiji KAJIHARA Kohei MIYASE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 2012-2020 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: low power, BIST, multi-cycle test, shift power,
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Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing Kohei MIYASE Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Yuta YAMATO Hiroshi FURUKAWA Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/06/01 Vol. E94-D No. 6 pp. 1216-1226 Type of Manuscript: PAPER Category: Dependable Computing Keyword: ATPG, X-bit, X-identification, X-filling,
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A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing Yuta YAMATO Xiaoqing WEN Kohei MIYASE Hiroshi FURUKAWA Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/04/01 Vol. E94-D No. 4 pp. 833-840 Type of Manuscript: PAPER Category: Dependable Computing Keyword: X-filling, genetic algorithm, launch switching activity, IR-drop, at-speed scan testing,
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A Study of Capture-Safe Test Generation Flow for At-Speed Testing Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1309-1318 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: at-speed scan testing, test generation, X-bit identification, X-filling, capture-safety checking,
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High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme Kohei MIYASE Xiaoqing WEN Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA Patrick GIRARD Laung-Terng WANG Mohammad TEHRANIPOOR
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/01/01 Vol. E93-D No. 1 pp. 2-9 Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs) Category: Keyword: power supply noise, test relaxation, X-filling, clock-gating, test compaction,
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A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Yuta YAMATO Yusuke NAKAMURA Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 667-674 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, X-fault model, per-test, via,
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On Detection of Bridge Defects with Stuck-at Tests Kohei MIYASE Kenta TERASHIMA Xiaoqing WEN Seiji KAJIHARA Sudhakar M. REDDY
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 683-689 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Defect-Based Testing Keyword: defect based testing, test vector generation, test vector modification, bridging faults, fault extraction,
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FOREWORD Seiji KAJIHARA Michiko INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 640-641 Type of Manuscript: FOREWORD Category: Keyword:
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A Novel ATPG Method for Capture Power Reduction during Scan Testing Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/09/01 Vol. E90-D No. 9 pp. 1398-1405 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2756-2765 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, per-test, X-fault model,
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On Finding Don't Cares in Test Sequences for Sequential Circuits Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2748-2755 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, don't care value, sequential circuit, stuck-at fault,
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A New Method for Low-Capture-Power Test Generation for Scan Testing Xiaoqing WEN Yoshiyuki YAMASHITA Seiji KAJIHARA Laung-Terng WANG Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1679-1686 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop,
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A Statistical Quality Model for Delay Testing Yasuo SATO Shuji HAMADA Toshiyuki MAEDA Atsuo TAKATORI Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 349-355 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Signal Integrity and Variability Keyword: delay testing, quality model, defect distribution,
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On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1671-1677 Type of Manuscript: PAPER Category: Dependable Computing Keyword: path delay fault, untestable path, potentially testable path, fault efficiency,
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On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 703-710 Type of Manuscript: PAPER Category: Computer Components Keyword: fault diagnosis, I_DDQ, transistor leakage fault model, multiple power supply, circuit partitioning,
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Don't Care Identification and Statistical Encoding for Test Data Compression Seiji KAJIHARA Kenjiro TANIGUCHI Kohei MIYASE Irith POMERANZ Sudhakar M. REDDY
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 544-550 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Test Generation and Compaction Keyword: test compression, don't care identification, Huffman's algorithm, test generation,
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Evaluation of Delay Testing Based on Path Selection Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA Shinichi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3208-3210 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: delay testing, path delay fault, path selection, untestable path,
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Average Power Reduction in Scan Testing by Test Vector Modification Seiji KAJIHARA Koji ISHIDA Kohei MIYASE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1483-1489 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test Generation and Modification Keyword: test power reduction, scan testing, ATPG, test modification,
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Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan Kenichi ICHINO Takeshi ASAKAWA Satoshi FUKUMOTO Kazuhiko IWASAKI Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1490-1497 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: hybrid BIST, unmodeled fault, n-detection test, partially rotational scan, at-speed testing,
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On Processing Order for Obtaining Implication Relations in Static Learning Hideyuki ICHIHARA Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/10/25 Vol. E83-D No. 10 pp. 1908-1911 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: test generation, implication, static learning,
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Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 pp. 861-867 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: retiming, logic synthesis, redundancy removal, test synthesis,
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Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis Seiji KAJIHARA Rikiya NISHIGAYA Tetsuji SUMIOKA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 pp. 811-816 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: test generation, multiple stuck-at fault, vector pair analysis, combinational circuit,
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A Reduced Scan Shift Method for Sequential Circuit Testing Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 pp. 2010-2016 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: sequential circuit, test generation, design for testability, scan circuit, reduced scan shift,
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Test Sequence Generation for Sequential Circuits with Distinguishing Sequences Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1730-1737 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: distinguishing sequence, stuck-at fault, sequential circuit, test sequence generation, design rechnique,
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