IEICE Trans

Satoshi OHTAKE

F-Scan: A DFT Method for Functional Scan at RTL Marie Engelene J. OBIEN Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/01/01 Vol. E94-D No. 1 pp. 104-113 Type of Manuscript: PAPER Category: Information Network Keyword: scan-based DFT, functional RTL circuits, high-level testing, assignment decision diagrams,
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A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification Hiroshi IWATA Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/07/01 Vol. E93-D No. 7 pp. 1857-1865 Type of Manuscript: PAPER Category: Information Network Keyword: false path, high level testing, path mapping, functional equivalence,
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Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors Masato NAKAZATO Michiko INOUE Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 763-770 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: software-based self-test, processor, test program template, design for testability, error masking, at-speed testing,
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Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability Masato NAKAZATO Satoshi OHTAKE Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 296-305 Type of Manuscript: PAPER Category: Dependable Computing Keyword: sequential circuit, test generation, synthesis for testability, finite state machine, test knowledge,
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A Design Scheme for Delay Testing of Controllers Using State Transition Information Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3200-3207 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: controller, delay fault, non-scan design, invalid test state and transition generator, at-speed test,
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Design for Two-Pattern Testability of Controller-Data Path Circuits Md. ALTAF-UL-AMIN Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/06/01 Vol. E86-D No. 6 pp. 1042-1050 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: design for testability, hierarchical testability, delay testing, controller-data path circuit, two-pattern testability,
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Design for Hierarchical Two-Pattern Testability of Data Paths Md. Altaf-Ul-AMIN Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/06/01 Vol. E85-D No. 6 pp. 975-984 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: design for testability, delay testing, hierarchical testability, two-pattern testability,
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