Satoshi ITO


A 12×16-Element Double-Layer Corporate-Feed Waveguide Slot Array Antenna
Satoshi ITO Miao ZHANG Jiro HIROKAWA Makoto ANDO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2016/01/01
Vol. E99-B  No. 1  pp. 40-47
Type of Manuscript:  Special Section PAPER (Special Section on Recent Progress in Antennas, Propagation and Wireless Systems Related to Topics in ISAP2014)
Category: Antennas and Propagation
Keyword: 
waveguide slot array antennacorporate-feed circuitcross-junction
 Summary | Full Text:PDF(3.8MB)

Postcopy Live Migration with Guest-Cooperative Page Faults
Takahiro HIROFUCHI Isaku YAMAHATA Satoshi ITOH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12  pp. 2159-2167
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Operating System
Keyword: 
virtual machinelive migrationpage faultpostcopy migration
 Summary | Full Text:PDF(2.1MB)

A WAN-Optimized Live Storage Migration Mechanism toward Virtual Machine Evacuation upon Severe Disasters
Takahiro HIROFUCHI Mauricio TSUGAWA Hidemoto NAKADA Tomohiro KUDOH Satoshi ITOH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12  pp. 2663-2674
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
disaster recoverylive migrationvirtual machinevirtual machine monitor
 Summary | Full Text:PDF(2.7MB)

Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme
Takuya YAGI Kunihiko USUI Tatsuji MATSUURA Satoshi UEMORI Satoshi ITO Yohei TAN Haruo KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/07/01
Vol. E94-C  No. 7  pp. 1233-1236
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
ADCself-calibrationpipelined ADCsplit ADCdigitally-assisted analog technology
 Summary | Full Text:PDF(603.1KB)

Design for Testability That Reduces Linearity Testing Time of SAR ADCs
Tomohiko OGAWA Haruo KOBAYASHI Satoshi UEMORI Yohei TAN Satoshi ITO Nobukazu TAKAI Takahiro J. YAMAGUCHI Kiichi NIITSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1061-1064
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
SAR ADCtestingDC linearitydesign for testabilitybuilt-in self-test
 Summary | Full Text:PDF(462.8KB)

100 nm-MOSFET Model for Circuit Simulation: Challenges and Solutions
Mitiko MIURA-MATTAUSCH Hiroaki UENO Hans Juergen MATTAUSCH Keiichi MORIKAWA Satoshi ITOH Akiyoshi KOBAYASHI Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/06/01
Vol. E86-C  No. 6  pp. 1009-1021
Type of Manuscript:  INVITED PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
Category: 
Keyword: 
MOSFET modelsurface potentialdevice phenomenaRF applications
 Summary | Full Text:PDF(1.6MB)

A Study on (1,7) Coded PRML Systems Using a Double Clock Weighted Viterbi Decoding for Optical Disc Recorder
Satoshi ITOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/04/25
Vol. E83-C  No. 4  pp. 652-658
Type of Manuscript:  PAPER
Category: Storage Technology
Keyword: 
(1,7) codepartial response equalizerViterbi decode
 Summary | Full Text:PDF(1.4MB)